FIGS. 1A and 1B illustrate a basic representation of a conventional field-effect transistor (FET) structure 100 in the prior art. The FET 100 includes two source/drain (S/D) regions 110, 120 (of a first conductivity type) formed on or in a substrate 130 (of a second conductivity type). A shallow trench isolation (STI) structure 140 isolates the FET 100 from other devices (not shown) formed on or in the substrate 130. A gate structure 150 overlies a portion of the substrate 130 and substantially defines a channel between one S/D region to the other. The “width” of the FET 100 is shown (FIGS. 1A, 1B) as extending along the longer dimension of the gate 150 (generally perpendicular to the flow of carrier(s) between the S/D regions.
Now referring to FIG. 1C, there is shown a graph depicting transistor gate width versus threshold voltage (Vt). As shown, Vt decreases as the gate width decreases. This is referred to as the narrow width effect. This presents a problem in nano-scale MOSFET devices and their design. As devices are scaled down, the narrowing of the gate width decreases Vt (assuming all other variables are unchanged). It will be understood that when devices are scaled, it may be possible that Vt increases, but in most scaling, it decreases. The decrease in Vt is caused by a combination of factors, including gate oxide thinning effect, doping depletion effect, gate wrap effect, stress effect, etc.
Prior art methods aimed at controlling the narrow width effect (i.e., increasing Vt) have focused on STI module optimization, but these methods have drawbacks—they are not straightforward, only minimally increase Vt, and are limited by reliability, tool availability and STI sharing among different applications.
Leading edge technologies used in fabricating nano-scale technologies commonly use raised S/D regions/structures in order to reduce S/D junction depth while maintaining or even reducing series resistance. Stress enhancement technologies, such as eSiGe for PFETs and SiC for NFETs can be used to form raised S/D regions.
Accordingly, there is a need for an improved fabrication process (and resulting devices) that increases the gate Vt of small scale FETs. By increasing the Vt of a narrow width devices while maintaining the Vt of nominal width devices, the narrow width effect can be minimized and FETs can be fabricated with smaller width dimensions with little or no decrease in Vt. Additionally, an improved fabrication process is needed to enable control (e.g., tune) of gate Vt in FETs. Such improved processes may be used in FETs with raised S/D regions.